1. Field of the Invention
The present invention is related to an improved arithmetic circuit for accumulative operation for use in digital signal processors, microprocessors and so forth, in which the pipelined control becomes effective during accumulative operation by eliminating idling stage in the pipeline.
2. Prior Art
In the accumulative operation for repeatedly performing a series of processing steps in a microprocessor with one cycle of operation being conducted by making use of the result of the previous cycle of operation, the overall processing speed is largely affected by the processing time required for the propagation of carries. For this reason, in the prior art technique, the processing speed for handling carries is conducted by making use of a CSA (Carry Save Adder) in advance of a CPA (Carry Propagation Adder), e.g., in the case that the operands are input with carries. The CSA is composed of a series of FAs (full adders) for high speed addition operation of three operands. One of the three operands is input to the carry-input terminals as carry-in signals while the resultant carry-out signals is output to the next stage rather than input to the adjacent FAs respectively. The final result can be obtained by 2-input adder, i.e., the CSA, provided for adding the outputs of the CSA.
On the other hand, the timing alignment between the two adders, i.e., the CPA and the CSA is established by making use of appropriate data latching circuits therebetween. The data latching circuits are required, for example, in the case that the operation time required in the CPA is relatively long as compared with the machine cycle time or in the case that the CPA is a circuit which operates under a certain timing restriction such as a precharge-type circuit.
In the following explanation, the operation of prior art arithmetic circuits provided with such data latching circuits will be explained with reference to the accumulative addition and the accumulative subtraction.
First of all, the prior art accumulative addition will be explained with reference to FIG. 1. As illustrated in FIG. 1, two input data operands Ai and Bi and the data latched on to an output register 32 are added, and the result is written to the output register 22. The result of the addition Ai+Bi is accumulated by repeating this process. Namely, the operation is performed as in the following equation.
(Initial Data)+(A0+B0)+(A1+B1)+ . . .
The two input data operands are given with a variety of applications. In one typical case, one input data A is comprised of carries while the other input data B is comprised of sums in a carry saved fashion for accumulative addition.
The accumulative adder comprises a selector circuit (multiplexer) 31 for selecting data to be loaded from arbitrary data and the outputs of the adder, an output register 32 for storing the outputs of the selector circuit 31, a CSA 33 for receiving the outputs of the output register 32 and input data operands Ai and Bi, intermediate result latching registers 34 and 35 for latching the outputs of the CSA 33 and a CPA 36 for receiving the outputs of the registers 34 and 35 as illustrated in FIG. 1.
Next, the arithmetic operation of the accumulative adder will be explained in the followings.
(Machine Cycle 1)
First of all, initial data is selected by the selector circuit 31 and written to the register 32 in order to load the initial data for addition.
(Machine Cycle 2)
In the next cycle, the CSA 33 performs the addition of the input data operands Ai and Bi and the outputs of the register 32 as input signals. The result of the addition is output as carries S1 and the sums S2 and latched on to the intermediate result latching register 34 respectively.
(Machine Cycle 3)
Next, the CPA 36 performs the addition of data as latched on to the register 34 and the register 35. The result of the addition as calculated by the CPA 36 is selected and written to the output register 32.
The addition operation is repeated by repeating the machine cycles 2 and 3.
Next, the prior art arithmetic circuit for accumulative subtraction will be explained with reference to FIG. 2.
The accumulative subtraction is performed by the subtraction formula.
(Initial Data)xe2x88x92(Input A0+Input B0)xe2x88x92(Input A1+Input B1) . . .
Also in this case, the operands are input in the form of carries and sums in which, for example, one input data operand Ai stands for carries while the other data operand Bi stands for sums in a carry saved fashion for accumulative subtraction, in the same manner as the addition circuit as described above. From the subtraction formula, the accumulative subtraction is represented by the following equation with input data Ai and Bi as a subtrahend and the initial data or the result of the previous accumulative subtraction as a minuend.       P1    -          (                        A          0                +                  B          0                    )        =                    P1        _            +              A        0            +              B        0              _  
Accordingly, the accumulative subtraction is realized by combination of an inverter and an adder.
The accumulative subtraction circuit is composed of a selector circuit 31 for selecting and outputting either of data to be loaded to the register 32 (the initial data) or the outputs of the adder, a register 32 for latching the outputs of the selector circuit 31, an inverter 37 for inverting the outputs of the register 32, a CSA 33 for receiving the outputs of the output register 32 and input data operands Ai and Bi, intermediate result latching register 34 and 35 for latching the carry and sums of the CSA 33, a CPA 36 for receiving the outputs of the registers 34 and 35 and an inverter 38 for inverting the outputs of the CPA as illustrated in FIG. 2.
Next, the arithmetic operation of the accumulative subtracter will be explained in the followings.
(Machine Cycle 1)
First of all, initial data is selected by the selector circuit 31 and written to the register 32 in order to load the initial data for addition.
(Machine Cycle 2)
In the next cycle, the CSA 33 performs the addition of the input data A and B and the inversion of the outputs of the register 32 as input signals in accordance with the following equation.
({overscore (P1)}+A0+B0)
The result of the addition is output as carries S1 and the sums S2 and latched on to the intermediate result latching register 34 and 35.
(Machine Cycle 3)
Next, the CPA 36 performs the addition of data as latched on to the register 34 and the register 35. The result of the addition as performed by the CPA 36 is inverted and outputted through the inverter 38. In this cycle, the selector circuit 31 selects the inversion of the output result of the CPA 36, followed by writing the operation result in accordance with the following equation to the register 32.   (                    P1        _            +              A        0            +              B        0              _    )
The subtraction operation is repeated by repeating the machine cycles 2 and 3, and after completing predetermined times of the repetition, the final result of the accumulative subtraction is obtained in the output register 32.
However, there are following shortcomings in the prior art accumulative arithmetic circuits as described above. These shortcomings will be explained with reference to FIG. 3. Namely, in the field to which the present invention pertains, pipelined control is usually implemented for the purpose of improving the processing speed of the operation. In the pipelined control, each instruction is divided into a plurality of the processing stages so that a plurality of instructions can be executed in parallel in different stages.
Namely, execution of one instruction can be initiated while the previous instruction is being executed.
However, the repetition of the prior art accumulative operation is possible only by reading and referring to the previous operation result. Namely, as illustrated in FIG.3 which shows a series of the accumulative addition operation (instruction 1, instruction 2, instruction 3 and so forth), each operation of the accumulative addition consists of the addition by the CSA (the first step) and the addition by the CPA (the second step), and therefore completed in two machine cycles. In accordance with the pipelined control, execution of an instruction 1 would be possible in advance of completing execution of an instruction 2. However, the contents of the output register have to be accessed to in he n-th cycle (n greater than 2) at time T22 or T32, only after completion of writing the result of the previous addition performed by the CPA to the output register in the second step, because the n-th cycle (n greater than 2) requires the result in the n-th cycle (n greater than 2). For this reason, the execution of the respective instructions are serialized so that there occur idling stages as depicted with arrows T21 and T31. As a result, much time is required to complete the accumulative operation.
As detailedly explained in the above, in accordance with the prior art technique, idling stages tend to occur in the pipelined structure so that the operation time as required increases resulting in deteriorating the performance of the processor.
The present invention has been made in order to solve the shortcomings as described above. It is an important object of the present invention to provide an improved arithmetic circuit for accumulative operation for use in digital signal processors, microprocessors and so forth, in which the next operation is initiated with intermediate results while the previous operation is being executed and not yet completed so that it is possible to reduce the scale of integration.
It is another associated object of the present invention to provide an improved arithmetic circuit for accumulative operation for use in digital signal processors, microprocessors and so forth, in which multiplication operation can be executed in parallel to accumulative operation having operand dependency upon the multiplication operation.
It is further associated object of the present invention to provide an improved arithmetic circuit for accumulative operation for use in digital signal processors, microprocessors and so forth, in which multiplication and accumulative subtraction can be effectively executed by dispensing with taking complement for intermediate results.
In brief, the above and other objects and advantages of the present invention are provided by a new and improved arithmetic circuit for accumulative operation comprises:
a first addition circuit for receiving and adding a plurality of input data operands and outputting two outputs of intermediate data of the addition; and
intermediate result latching means for receiving and latching said two outputs of intermediate data as first and second intermediate results,
wherein in the case that addition is performed by the use of the previous result of the accumulative operation, the two outputs of intermediate data of the addition calculated by said first addition circuit and latched on to said intermediate result latching means are supplied to said first addition circuit as two of said input data operands for next operation of accumulative addition to be conducted by said first addition circuit.
Also, in accordance with a preferred embodiment of the present invention, the accumulative operation is initiated by supplying two arbitrary data operands of initial data to said first addition circuit in place of the two outputs of intermediate data of the addition.
Furthermore, in accordance with a preferred embodiment of the present invention, said first addition circuit receives said input data operands through a first selector for selectively supplying either of said first intermediate result as latched on to said intermediate result latching means or one of said arbitrary data operands of said initial data, and a second selector for selectively supplying either of said second intermediate result as latched on to one of said intermediate result latching means or an all zero data operand.
Furthermore, in accordance with a preferred embodiment of the present invention, said first addition circuit is an addition circuit comprising a 4-2 compactor.
In accordance with a further aspect of the present invention, a new and improved arithmetic circuit for accumulative operation comprises:
a first addition circuit for receiving and adding a plurality of input data operands and outputting two outputs of intermediate data of the addition; and
intermediate result latching means for receiving and latching said two outputs of intermediate data as first and second intermediate results,
wherein in the case that the plurality of input data operands are added up together and subtracted from initial data given as a minuend, the inversion of said initial data is given to said first addition circuit and added up together with the input data operands as externally supplied, and the two outputs of intermediate data are latched on to said intermediate result latching means, and wherein in the case that the plurality of input data operands are added up together and subtracted from the results of the previous operation as a minuend, the two outputs of intermediate data of the addition calculated by said first addition circuit and latched on to said intermediate result latching means are supplied to said first addition as two of said input data operands for next accumulative operation to be conducted by said first addition circuit, and the accumulative operation is repeated for predetermined times while the result of accumulative subtraction is obtained by adding up together the two outputs of intermediate data and inverting the result of the addition.
Furthermore, in accordance with a preferred embodiment of the present invention, the arithmetic circuit for accumulative operation further comprises:
a second addition circuit connected to said intermediate result latching means for adding up said first and second intermediate results as latched on to said intermediate result latching means and outputting a result of addition;
a first inverter connected to said second addition circuit for inverting output data of said second addition circuit;
a second inverter for outputting the inversion of arbitrary initial data;
a second selector for selectively outputting to said first addition circuit either of said first intermediate result and the inversion of the inversion of arbitrary initial data;
wherein the two outputs of intermediate data of the addition calculated by said first addition circuit and latched on to said intermediate result latching means are supplied to said first addition as two of said input data operands for next accumulative operation to be conducted by said first addition circuit.
Furthermore, in accordance with a preferred embodiment of the present invention, the arithmetic circuit for accumulative operation further comprises:
a third selector connected to said first addition circuit and another of said intermediate result latching means for selectively outputting to said first addition circuit either of said first intermediate result and all zero data.
In accordance with a further aspect of the present invention, a new and improved arithmetic circuit for accumulative operation comprises:
an addition circuit for receiving and adding a plurality of input data operands and outputting two outputs of intermediate data of the addition; and
intermediate result latching means for receiving and latching said two outputs of intermediate data as first and second intermediate results,
wherein the plurality of input data operands are supplied to added up together by said addition circuit and the two outputs of intermediate data are latched on to said intermediate result latching means,
wherein the inversion of the two outputs of intermediate data of the addition calculated by said first addition circuit and latched on to said intermediate result latching means are supplied to said addition circuit and added up together with the plurality of input data operands supplied as a minuend, and the result of the addition is latched on to said intermediate result latching means,
and wherein the two outputs of intermediate data of the addition latched on to said intermediate result latching means are added up, and the result is incremented by 1 and inverted to obtain the final result of the operation.
Also, in accordance with a preferred embodiment of the present invention, in the case that the plurality of input data operands are added up together and subtracted from the results of the previous operation as a minuend, the two outputs of intermediate data latched on to said intermediate result latching means are supplied to said addition circuit and added up together with the plurality of input data operands as a minuend, and the accumulative operation is repeated for predetermined times while the result of accumulative subtraction is obtained by adding up together the two outputs of intermediate data and incrementing the result by 1.
In accordance with a further aspect of the present invention, a new and improved arithmetic circuit for accumulative operation comprises:
a multiplication circuit for generating a multiplication result of a multiplier and a multiplicand in the form of sums and carries;
a first addition circuit for receiving and adding a plurality of input data operands including said sums and said carries and outputting two outputs of intermediate data of the addition; and
intermediate result latching means for receiving and latching said two outputs of intermediate data as first and second intermediate results,
wherein in the case that multiplication and accumulative addition is repeated by the use of the previous result of the accumulative operation, the two outputs of intermediate data of the addition calculated by said first addition circuit and latched on to said intermediate result latching means are supplied to said first addition as two of said input data operands for next multiplication and accumulative addition to be conducted by said first addition circuit.
In accordance with a further aspect of the present invention, a new and improved arithmetic circuit for accumulative operation comprises:
a multiplication circuit for generating a multiplication result of a multiplier and a multiplicand in the form of sums and carries;
a first addition circuit for receiving and adding a plurality of input data operands including said sums and said carries and outputting two outputs of intermediate data of the addition: and
intermediate result latching means for receiving and latching said two outputs of intermediate data as first and second intermediate results,
wherein the first and second intermediate results are added up together and subtracted from the results of the previous operation as a minuend,
wherein, in the case that initial data is given as minuend, the inversion of arbitrary initial data is supplied to said first addition circuit and added up together with sums and carries as supplied from said multiplication circuit, and the two outputs of said first addition circuit are latched on to said intermediate result latching means as first and second intermediate results,
wherein, in the case that subtraction is repeated, said first and second intermediate results as latched on to said intermediate result latching means are supplied to said first addition circuit as two of said input data operands for next operation and repeating the supply to said first addition circuit, and
wherein the result of accumulative subtraction is obtained by adding up together the two outputs of intermediate data and incrementing the result by 1.
Furthermore, in accordance with a preferred embodiment of the present invention, the arithmetic circuit for accumulative operation further comprises:
a first inverter connected to said second addition circuit for inverting output data of said second addition circuit;
a first selector receiving an initial data and connected to said first inverter for selectively outputting either of said initial data and the inversion of the output data of said second addition circuit as inverted by said first inverter;
resultant data latching means connected to said first selector for latching either of said initial data and the inversion of the output data of said second addition circuit as inverted by said first inverter;
a second inverter connected to said resultant data latching means for outputting the inversion of the output data of resultant data latching means;
a third inverter connected to one of said intermediate result latching means for outputting the inversion of said first intermediate result;
a second selector connected to said first addition circuit, said second inverter, said third inverter and one of said intermediate result latching means for selectively outputting to said first addition circuit either of said first intermediate result, the inversion of said first intermediate result as inverted by said third inverter and the inversion of the output data of said second addition circuit as inverted by said first inverter.
Furthermore, in accordance with a preferred embodiment of the present invention, the arithmetic circuit for accumulative operation further comprises:
a fourth inverter connected to another of said intermediate result latching means for outputting the inversion of said second intermediate result;
a third selector connected to said first addition circuit and another of said intermediate result latching means for selectively outputting to said first addition circuit either of said second intermediate result, the inversion of said second intermediate result as inverted by said third inverter and all zero data.
Furthermore, in accordance with a preferred embodiment of the present invention, the arithmetic circuit for accumulative operation further comprises:
a first inverter for inverting output data of a second addition circuit connected to said intermediate result latching means for adding up said first and second intermediate results as latched on to said intermediate result latching means and outputting a result of addition;
a second inverter for outputting the inversion of arbitrary initial data; and
a second selector for selectively supplying to said first addition circuit either of the output data of one of said intermediate result latching means and the output data of said second inverter.
Furthermore, in accordance with a preferred embodiment of the present invention, the arithmetic circuit for accumulative operation further comprises:
a second addition circuit for adding up said first and second intermediate results as latched on to said intermediate result latching means and outputting a result of addition; and
a first inverter connected to said second addition circuit for inverting output data of said second addition circuit;
a second inverter for outputting the inversion of arbitrary initial data;
a third inverter for outputting the inversion of said first intermediate result;
a second selector for selectively outputting to said first addition circuit either of the inversion of arbitrary initial data, the output data of one of said intermediate result latching means and said first intermediate result.
In accordance with a further aspect of the present invention, a new and improved arithmetic circuit for accumulative operation comprises:
a multiplication circuit for generating a multiplication result of a multiplier and a multiplicand in the form of sums and carries;
a first addition circuit for receiving and adding a plurality of input data operands including said sums and said carries and outputting two outputs of intermediate data of the addition; and
intermediate result latching means for receiving and latching said two outputs of intermediate data as first and second intermediate results,
wherein the sums and carries obtained as the results of the multiplication are supplied to said first addition circuit and the two outputs of intermediate data of the addition calculated by said first addition circuit are latched on to said intermediate result latching means, and
wherein the two outputs of the intermediate result latching means are inverted and supplied to supplied to said first addition circuit as two of said input data operands for next operation, the addition of the sums and carries obtained as supplied from said multiplication circuit is performed, the two intermediate results thereof are latched on to said intermediate result latching means and added up together with the two outputs of intermediate data of the addition calculated by said first addition circuit, incremented by 1 and inverted to obtain the result of the multiplication and accumulative subtraction.
Also, in the case that the accumulative subtraction is performed with the result of the previous multiplication operation as a subtrahend and the result of the previous subtraction operation as a minuend, the two outputs as latched on to said intermediate result latching means are supplied to said first addition circuit as two of said input data operands for next accumulative operation to be conducted by said first addition circuit in place of said two inversion results and added up together with sums and carries as supplied from said multiplication circuit, and the two outputs of said first addition circuit are latched on to said intermediate result latching means followed by repetition of these procedures for predetermined times, and wherein the two outputs of intermediate data of the addition circuit latched on to said intermediate result latching means are added up, and the result is incremented by 1 and inverted to obtain the final result of the operation.
Also, in accordance with a preferred embodiment of the present invention, the two outputs of intermediate data of the addition circuit latched on to said intermediate result latching means are added up by means of a carry propagation adder, as a second addition circuit, while the increment of 1 is performed as a carry-in signal.
Furthermore, in accordance with a preferred embodiment of the present invention, the arithmetic circuit for accumulative operation further comprises:
a first inverter connected to said second addition circuit for inverting output data of said second addition circuit;
a first selector receiving an initial data and connected to said first inverter for selectively outputting either of said initial data and the inversion of the output data of said second addition circuit as inverted by said first inverter;
resultant data latching means connected to said first selector for latching either of said initial data and the inversion of the output data of said second addition circuit as inverted by said first inverter;
a second inverter connected to said resultant data latching means for outputting the inversion of the output data of resultant data latching means;
a third inverter connected to one of said intermediate result latching means for outputting the inversion of said first intermediate result;
a second selector connected to said first addition circuit, said second inverter, said third inverter and one of said intermediate result latching means for selectively outputting to said first addition circuit either of said first intermediate result, the inversion of said first intermediate result as inverted by said third inverter and the inversion of the output data of said second addition circuit as inverted by said first inverter.
Also, in accordance with a preferred embodiment of the present invention, the arithmetic circuit for accumulative operation further comprises:
a fourth inverter connected to another of said intermediate result latching means for outputting the inversion of said second intermediate result;
a third selector connected to said first addition circuit and another of said intermediate result latching means for selectively outputting to said first addition circuit either of said second intermediate result, the inversion of said second intermediate result as inverted by said third inverter and all zero data.
In accordance with a further aspect of the present invention, a new and improved arithmetic circuit for accumulative operation comprises:
a multiplication circuit for generating a multiplication result of a multiplier and a multiplicand in the form of sums and carries;
a first addition circuit for receiving and adding a plurality of input data operands including said sums and said carries as outputs from said multiplication circuit and the inversion of said sums and said carries as a result of the previous multiplication conducted by said multiplication circuit and outputting two outputs of intermediate data of the addition circuit; and
intermediate result latching means for receiving and latching said two outputs of intermediate data as first and second intermediate results,
wherein the first and second intermediate results are added up together and incremented by 1 and inverted to obtain the final result of the operation.
In brief, the above and other objects and advantages of the present invention are provided by a new and improved arithmetic circuit for accumulative operation capable of multiplication and accumulative addition and multiplication and accumulative subtraction comprises:
a multiplication circuit for generating a multiplication result of a multiplier and a multiplicand in the form of sums and carries;
a first addition circuit for receiving and adding a plurality of input data operands including said sums and said carries and outputting two outputs of intermediate data of the addition circuit; and
intermediate result latching means for receiving and latching said two outputs of intermediate data as first and second intermediate results,
wherein said sums and said carries as a result of initial multiplication conducted by said multiplication circuit are supplied to said first addition circuit and the two outputs of intermediate data of the addition calculated by said first addition circuit are latched on to said intermediate result latching means,
wherein, in the case that the multiplication and accumulative addition is performed, the results latched on to said intermediate result latching means are supplied to said first addition circuit as two of said input data operands for next accumulative operation and added up together with sums and carries as supplied from said multiplication circuit; the two outputs of said first addition circuit are latched on to said intermediate result latching means and added up together with the next data latched on to said intermediate result latching means to obtain the final result of the multiplication and accumulative addition operation, and
wherein, in the case that the multiplication and accumulative subtraction is performed, the results latched on to said intermediate result latching means are inverted and supplied to said first addition circuit as two of said input data operands for next accumulative operation and added up together with sums and carries as supplied from said multiplication circuit, and the two outputs of said first addition circuit are latched on to said intermediate result latching means and added up together with the next data latched on to said intermediate result latching means and incremented by 1 and inverted to obtain the final result of the multiplication and accumulative subtraction operation.
Also, in the case that accumulative operation is repeated, the results latched on to said intermediate result latching means are inverted and supplied to said first addition circuit as two of said input data operands for next accumulative operation, and the two outputs of said first addition circuit are added up together and incremented by 1 and inverted to obtain the final result of the accumulative operation
In accordance with a further aspect of the present invention, a new and improved arithmetic circuit for accumulative operation comprises:
a first addition circuit for receiving and adding a plurality of input data operands and outputting two outputs of intermediate data of the addition;
intermediate result latching means connected to said first addition circuit for receiving and latching said two outputs of intermediate data as first and second intermediate results; and
a second addition circuit for adding up said first and second intermediate results as latched on to said intermediate result latching means and outputting a result of addition;
wherein the two outputs of intermediate data of the addition calculated by said first addition circuit and latched on to said intermediate result latching means are supplied to said first addition as two of said input data operands for next operation of accumulative addition to be conducted by said first addition circuit.
Also, in accordance with a preferred embodiment of the present invention, the accumulative operation is initiated by supplying two arbitrary data operands of initial data to said first addition circuit in place of the two outputs of intermediate data of the addition.
Furthermore, in accordance with a preferred embodiment of the present invention, at least one of said arbitrary data operands of said initial data supplied to said first addition circuit is all zero data.
Furthermore, in accordance with a preferred embodiment of the present invention, one of said arbitrary data operands is latched on to said resultant data latching means in advance.
Furthermore, in accordance with a preferred embodiment of the present invention, said two outputs of intermediate data of the addition are carries and sums.
Furthermore, in accordance with a preferred embodiment of the present invention, said first addition circuit receives said input data operands through a first selector for selectively supplying either of said first intermediate result as latched on to said intermediate result latching means or one of said arbitrary data operands of said initial data, and a second selector for selectively supplying either of said second intermediate result as latched on to one of said intermediate result latching means or an all zero data operand.
Furthermore, in accordance with a preferred embodiment of the present invention, said first addition circuit is an addition circuit comprising a 4-2 compactor.
In accordance with a further aspect of the present invention, a new and improved arithmetic circuit for accumulative operation comprises:
a first addition circuit for receiving and adding a plurality of input data operands and outputting two outputs of intermediate data of the addition;
intermediate result latching means for receiving and latching said two outputs of intermediate data as first and second intermediate results;
a second addition circuit connected to said intermediate result latching means for adding up said first and second intermediate results as latched on to said intermediate result latching means and outputting a result of addition;
a first inverter connected to said second addition circuit for inverting output data of said second addition circuit;
a second inverter for outputting the inversion of arbitrary initial data;
a second selector for selectively outputting to said first addition circuit either of said first intermediate result and the inversion of the inversion of arbitrary initial data;
wherein the two outputs of intermediate data of the addition calculated by said first addition circuit and latched on to said intermediate result latching means are supplied to said first addition as two of said input data operands for next accumulative operation to be conducted by said first addition circuit.
Furthermore, in accordance with a preferred embodiment of the present invention, the arithmetic circuit for accumulative operation further comprises:
a third selector connected to said first addition circuit and another of said intermediate result latching means for selectively outputting to said first addition circuit either of said first intermediate result and all zero data;
In accordance with a further aspect of the present invention, an arithmetic circuit for accumulative operation comprising:
a multiplier for generating a multiplication result of a multiplier and a multiplicand in the form of sums and carries;
a first addition circuit connected to said multiplier for receiving and adding a plurality of input data operands including said sums and said carries and outputting two outputs of intermediate data of the addition;
intermediate result latching means connected to said first addition circuit for receiving and latching said two outputs of intermediate data as first and second intermediate results;
a second addition circuit connected to said intermediate result latching means for adding up said first and second intermediate results as latched on to said intermediate result latching means and outputting a result of addition;
wherein the two outputs of intermediate data of the addition calculated by said first addition circuit and latched on to said intermediate result latching means are supplied to said first addition as two of said input data operands for next accumulative operation to be conducted by said first addition circuit.
Furthermore, in accordance with a preferred embodiment of the present invention, the arithmetic circuit for accumulative operation further comprises:
a first inverter for inverting output data of a second addition circuit connected to said intermediate result latching means for adding up said first and second intermediate results as latched on to said intermediate result latching means and outputting a result of addition;
a second inverter for outputting the inversion of arbitrary initial data; and
a second selector for selectively supplying to said first addition circuit either of the output data of one of said intermediate result latching means and the output data of said second inverter.
Furthermore, in accordance with a preferred embodiment of the present invention, the arithmetic circuit for accumulative operation further comprises:
a second addition circuit for adding up said first and second intermediate results as latched on to said intermediate result latching means and outputting a result of addition; and
a first inverter connected to said second addition circuit for inverting output data of said second addition circuit;
a second inverter for outputting the inversion of arbitrary initial data;
a third inverter for outputting the inversion of said first intermediate result;
a second selector for selectively outputting to said first addition circuit either of the inversion of arbitrary initial data, the output data of one of said intermediate result latching means and said first intermediate result.
Furthermore, in accordance with a preferred embodiment of the present invention, the arithmetic circuit for accumulative operation further comprises:
a third selector for selectively supplying to said first addition circuit either of the output of another of said intermediate result latching means and all zero data;
Furthermore, in accordance with a preferred embodiment of the present invention, the arithmetic circuit for accumulative operation further comprises:
a fourth inverter for outputting the inversion of said second intermediate result;
a third selector connected to said first addition circuit and another of said intermediate result latching means for selectively outputting to said first addition circuit either of said second intermediate result, the inversion of said second intermediate result as inverted by said third inverter and all zero data.
Other and further objects and features of the present invention will become obvious upon an understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.